| 发明名称 | Semiconductor memory apparatus | ||
| 摘要 | A semiconductor memory apparatus may include a decoding control block configured to generate a first decoding control signal and a second decoding control signal in response to a double enable signal and a first address. The semiconductor memory apparatus may include a decoding block configured to enable only one word line among a plurality of word lines or may simultaneously enable at least two word lines among the plurality of word lines, in response to the first and second decoding control signals and a second address. | ||
| 申请公布号 | US9570136(B2) | 申请公布日期 | 2017.02.14 |
| 申请号 | US201514668379 | 申请日期 | 2015.03.25 |
| 申请人 | SK HYNIX INC. | 发明人 | Song Choung Ki |
| 分类号 | G11C7/00;G11C8/18;G11C8/10 | 主分类号 | G11C7/00 |
| 代理机构 | William Park & Associates Ltd. | 代理人 | William Park & Associates Ltd. |
| 主权项 | 1. A semiconductor memory apparatus comprising: a decoding control block configured to generate a first decoding control signal and a second decoding control signal in response to a double enable signal and a first address; and a decoding block configured to enable only one word line among a plurality of word lines or simultaneously enable at least two word lines among the plurality of word lines, in response to the first and second decoding control signals and a second address. | ||
| 地址 | Icheon-si KR | ||