Non-volatile memory serial core architecture

摘要

A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

主权项

1. A memory system comprising:
a memory bank including
a first page buffer coupled to bitlines, the first page buffer having a sequential enabler for shifting a first logic level to select a first group of the bitlines for providing read data in parallel in response to a read operation and for receiving write data in parallel in response to a write operation,and a parallel/serial data converter for converting the read data into serial bitstream read data and for converting serial bitstream write data into the write data; and, a serial data path for coupling the serial bitstream read data and the serial bitstream write data between the memory bank and an input/output interfacewherein the memory bank includes:
a first bank half coupled to first n parallel datalines for receiving the read data from the first page buffer, where n is an integer value greater than 0, a second bank half coupled to second n parallel datalines, and the parallel/serial data converter is configured to selectively convert one of the first and the second n parallel datalines into the serial bitstream read data, and for selectively converting the serial bitstream write data into parallel data for one of the first and the second n parallel datalinesand wherein the parallel/serial data converter includes:
a first parallel/serial data converter for sequentially coupling each of the first n parallel datalines to a first terminal, a second parallel/serial data converter for sequentially coupling each of the second n parallel datalines to a second terminal, and a data path selector for selectively coupling one of the first terminal and the second terminal to a bidirectional serial data line.