发明名称 Semiconductor device, memory device, and electronic device
摘要 To provide a small, highly reliable memory device with a large storage capacity. A semiconductor device includes a circuit for retaining data and a circuit for reading data. The circuit for retaining data includes a transistor and a capacitor. The circuit for reading data is configured to supply a potential to the circuit for retaining data and read a potential from the circuit for retaining data. The circuit for retaining data and the circuit for reading data are provided in different layers, so that the semiconductor device with a large storage capacity is manufactured.
申请公布号 US9570116(B2) 申请公布日期 2017.02.14
申请号 US201514963434 申请日期 2015.12.09
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Kato Kiyoshi
分类号 G11C5/06;G11C11/419;G11C7/10;G11C11/24;G11C11/4096;G11C11/4094;G11C5/14;G11C5/10;G11C11/4091;G11C11/4074 主分类号 G11C5/06
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A semiconductor device comprising a first circuit, the first circuit comprising a first input terminal, a first output terminal, a first transistor, and a second circuit, and the second circuit comprising a second to a (2n+1)th transistor, a first to an n-th capacitor, a first to an n-th wiring, a first gate wiring, and a first to an n-th storage node (n is an integer of 2 or more), wherein a gate of the 2i-th transistor is electrically connected to the first gate wiring (i is an integer of 1 to n), wherein a first terminal of the 2i-th transistor is electrically connected to a gate of the (2i+1)th transistor and a first terminal of the i-th capacitor through the i-th storage node, wherein the first wiring is electrically connected to a second terminal of the first transistor, wherein the i-th wiring is electrically connected to a second terminal of the 2i-th transistor, wherein the first input terminal is electrically connected to a first terminal of the first transistor, wherein a second terminal of the first transistor is electrically connected to a first terminal of the third transistor, wherein a second terminal of a (2i−1)th transistor is electrically connected to a first terminal of the (2i+1)th transistor, and wherein a second terminal of the (2n+1)th transistor is electrically connected to the first output terminal.
地址 Atsugi-shi, Kanagawa-ken JP