SAR ADC performance optimization with dynamic bit trial settings

摘要

An analog-to-digital converter (ADC) circuit comprises a digital-to-analog (DAC) circuit including at least N+n weighted circuit components, wherein N and n are positive integers greater than zero, and n is a number of repeat bits of the least significant bit (LSB) of the ADC circuit; a sampling circuit configured to sample an input voltage at an input to the ADC circuit and apply a sampled voltage to the weighted circuit components; a comparator circuit configured to compare an output voltage of the DAC to a specified threshold voltage during a bit trial; and logic circuitry configured to perform bit trials for the at least N+n weighted circuit components and adjust one or more parameters for one or more of N bit trials according to values of the n LSB repeat bits.

主权项

1. An analog-to-digital converter (ADC) circuit comprising:
a digital-to-analog (DAC) circuit including at least N+n weighted circuit components, wherein N and n are positive integers greater than zero, and n is a number of repeat bits of the least significant bit (LSB) of the ADC circuit; a sampling circuit configured to sample an input voltage at an input to the ADC circuit and apply a sampled voltage to the weighted circuit components; a comparator circuit configured to compare an output voltage of the DAC to a specified threshold voltage during a bit trial; and logic circuitry configured to perform bit trials for the at least N+n weighted circuit components and adjust one or more parameters for one or more of N bit trials according to values of the n LSB repeat bits.