发明名称 |
Method for fabricating electronic devices having semiconductor memory unit |
摘要 |
Devices and method based on disclosed technology include, among others, a method for capable of providing asymmetrical arrangement of hole patterns while improving non-uniformity of an electronic device. Specifically, a method for fabricating hole patterns in one implementation includes forming a mask pattern which is defined with hole patterns of an asymmetrical arrangement with different longitudinal and transverse intervals, over a layer to be etched; and etching the layer to be etched, using the mask pattern as an etch barrier. |
申请公布号 |
US9570680(B2) |
申请公布日期 |
2017.02.14 |
申请号 |
US201314145782 |
申请日期 |
2013.12.31 |
申请人 |
SK hynix Inc. |
发明人 |
Kim Jae-Heon;Lee Sung-Koo |
分类号 |
H01L21/461;H01L45/00;H01L21/027;H01L21/033;H01L21/311;H01L43/08;H01L27/22;H01L27/24;H01L21/768 |
主分类号 |
H01L21/461 |
代理机构 |
Perkins Coie LLP |
代理人 |
Perkins Coie LLP |
主权项 |
1. A method for fabricating an electronic device having a semiconductor memory unit, comprising:
forming a mask pattern which is defined with hole patterns of an asymmetrical arrangement with different longitudinal and transverse intervals, over an etch target layer; and etching the etch target layer, using the mask pattern as an etch barrier, wherein the forming of the mask pattern comprises: forming a photoresist pattern with a plurality of openings which are defined by first regions where optical processing is performed and second regions where optical processing is not performed over a sacrificial layer; forming a gap filling layer to fill or cover the openings defined by the second regions of the photoresist pattern; and etching the sacrificial layer using the first regions of the photoresist pattern and the gap filling layer as etch barriers, and forming a sacrificial pattern which is defined with the hole patterns of the asymmetrical arrangement with the different longitudinal and transverse intervals. |
地址 |
Icheon-Si KR |