发明名称 Multi-stage interconnect network in a parallel processing network device
摘要 A packet is received at a packet processing element, among a plurality of like packet processing elements, of a network device, and request specifying a processing operation to be performed with respect to the packet by an accelerator engine functionally different from the plurality of like packet processing elements is generated by the packet processing element. The request is transmitted to an interconnect network that includes a plurality of interconnect units arranged in stages. A path through the interconnect network is selected among a plurality of candidate paths, wherein no path of the candidate paths includes multiple interconnect units within a same stage of the interconnect network. The request is then transmitted via the determined path to a particular accelerator engine among multiple candidate accelerator engines configured to perform the processing operation. The processing operation is then performed by the particular accelerator engine.
申请公布号 US9571380(B2) 申请公布日期 2017.02.14
申请号 US201414482980 申请日期 2014.09.10
申请人 Marvell World Trade Ltd. 发明人 Kadosh Aviran;Zemach Rami
分类号 H04L12/26;H04L12/715;H04L12/803;H04L12/933;H04L12/931 主分类号 H04L12/26
代理机构 代理人
主权项 1. A method, comprising: receiving a packet at a packet processing element, among a plurality of like packet processing elements, of a network device; generating, by the packet processing element, a request specifying a processing operation to be performed with respect to the packet by an accelerator engine functionally different from the plurality of like packet processing elements; transmitting the request from the packet processing element to an interconnect network, the interconnect network including a plurality of interconnect units arranged in stages; determining a path through the interconnect network, wherein the path is selected among a plurality of candidate paths, wherein no path of the candidate paths includes multiple interconnect units within a same stage of the interconnect network; transmitting the request, via the determined path, to a particular accelerator engine among multiple candidate accelerator engines configured to perform the processing operation; and performing the processing operation by the particular accelerator engine.
地址 St. Michael BB