Method for etching high-K dielectric using pulsed bias power

摘要

A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

主权项

1. A method of patterning etching a layer on a substrate, comprising:
disposing a substrate in a plasma processing system; and transferring a pattern to at least one layer on said substrate using a pulsed plasma etching process, said pulsed plasma etching process comprising:
introducing a flow of a process gas composition to said plasma processing system,generating plasma in said plasma processing system,electrically biasing a substrate holder that supports said substrate with radio frequency (RF) power, andmodulating said RF power for said electrical biasing, or a flow of said process composition, or both said RF power for said electrical biasing and said flow of said process composition,wherein said modulating said RF power for said electrical biasing further comprises:modulating said RF power at a first RF power level for a first time duration; andmodulating said RF power at a second RF power level for a second time duration, wherein said second RF power level is less than said first RF power level, and said second time duration follows said first time duration.