Structure and method for testing stacked CMOS structure

摘要

A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.

主权项

1. A test structure for testing a 3D semiconductor structure having a plurality of tiers, comprising
at least one conductive loop, each respective conductive loop comprising two pairs of ends in a top tier of the plurality of tiers and being embedded inside two or more of the plurality of tiers in the semiconductor structure, a first pair of ends and a second pair of ends being in a same loop and each defining one opening therebetween; and at least two test pads on each respective conductive loop, the at least two test pads electrically connected with respective ends of each respective conductive loop, wherein each respective conductive loop comprises at least one conductive ring in the two or more of the plurality of tiers; and the respective conductive rings in at least two of the plurality of tiers are electrically connected with each other through inter-level vias across two adjacent tiers of the plurality of tiers and through the second pair of ends in the top tier to form the respective conductive loop.