Transition delay detector for interconnect test

摘要

A test circuitry is configured to test for transition delay defects in a first inter-die interconnect connecting a first die and a second die. A test data value is initially received and temporarily stored in a data storage element. The test data is subsequently looped between the storage element and the second die through a feedback loop including the first inter-die interconnect and a second inter-die interconnect. A data conditioner conditions the test data value received from the second die so as to make it distinguishable from the test data value sent to the second die. A clock pulse generator generates a delayed clock pulse. A selection logic applies the generated delayed clock pulse and the conditioned fed back test data value to the data storage element. A readout unit for reading out a test data value stored in the data storage element.

主权项

1. A test circuitry configured to test for transition delay defects in a first inter-die interconnect electrically connecting a first die and a second die to one another, the test circuitry comprising:
an input port configured to receive a test data value; a data storage element having a data input and a clock input and configured to temporarily store the test data value; a second inter-die interconnect configured to be electrically connected to the first inter-die interconnect so as to form a feedback loop through which the test data value is looped, the feedback loop configured such that the test data value is sent from the data storage element to the second die through the first inter-die interconnect, and sent back from the second die to the data storage element through the second inter-die interconnect; a data conditioner configured to condition the test data value sent back from the second die to the first die so as to make it distinguishable from the stored test data value; a clock pulse generator configured to generate a delayed clock pulse; a selection logic comprising a first multiplexer configured to provide alternative inputs comprising an externally applied test data signal and a loopback test data that has travelled through the feedback loop to the data input of the data storage element; the selection logic further comprising a second multiplexer configured to provide alternative inputs comprising an externally generated clock signal and the delayed clock pulse to the clock input of the data storage element, wherein the selection logic is configured to provide the delayed clock pulse when the test data value is looped, and wherein the test circuitry is configured such that a determination of whether or not the transition delay defects are present is made at least in part by comparing relative arrival times at the storage element of the delayed clock pulse and the loopback test data; and a readout unit for reading out a test data value stored in the data storage element.