Circuit and method of adaptive filtering digital calibration of ADC

摘要

An adaptive filtering digital calibration circuit of ADC, which includes a control module, a fixed-point adder, and a fixed-point multiplier; the control module includes a finite-state machine, a shift register, and a register array; the fixed-point adder allows an addend and an augend to be added together after being encoded; the control module controls to complete all the calibration algorithmic operation, which includes the following steps: the control module controls to obtain an original binary value from an external ADC; calculating an error value according to weight and disturbance signals, and carrying out the weight updating operation and the disturbance signal updating operation according to the error value; carrying out the gain calibration operation; and carrying out the final result operation. The present invention also discloses a method of the adaptive filtering digital calibration of ADC.

主权项

1. An adaptive filtering digital calibration circuit of ADC (Analog to Digital Converter), the adaptive filtering digital calibration circuit comprising a control module, a plurality of fixed-point adders, and a fixed-point multiplier; the control module comprising a finite-state machine, a shift register, and a register array;
wherein the plurality of the fixed-point adders are used for parallel addition operation, with each of the plurality of the fixed-point adders including three input terminals and two output terminals, respectively, the three input terminals being used for inputting an addend, an augend and a data encoding indication signal, respectively, a first output terminal used for outputting a data overflow indication signal, the other output terminal being used for outputting an addition result; the data encoding indication signal provided by the finite-state machine and includes four bits, the addend and the augend are changed in format under control of a two-bit signal of the data encoding indication signal, respectively, and one of the plurality of the fixed-point adders carries out an addition operation on the addend and the augend after the change in format; the control module controls an operational state of the adaptive filtering digital calibration circuit and controls to complete all calibration algorithmic operation, which includes: Step 1: the control module obtains a first original binary value from an external ADC and: (a) when a calibration enable signal is in an enable state, the control module obtains a second original binary value from the external ADC and proceeds to Step 2; (b) when the calibration enable signal is in a disable state, the control module obtains the first original binary value and skips Steps 2 and 3 and proceeds directly to Step 4; Step 2: calculating an error value according to weight and disturbance signals, and carrying out a weight updating operation and a disturbance signal updating operation according to the error value; judging whether the weight updating operation has been carried out for M times, wherein M is greater than 1; if the weight updating operation is carried out less than M times, Step 1 will be carried out again; if the weight updating operation has been carried out for M times, it is judged whether the error value is less than 2 LSB; if the error value is less than 2 LSB, a gain calibration operation is carried out, with the updated weight as an optimal weight, and then proceed to Step 3; otherwise a high pulse of one cycle is outputted at an “error” port of the control module and all the calibration algorithmic operations are terminated; Step 3: carrying out a gain calibration operation by first calculating an optimal weight sum based on the optical weight in Step 2, then carrying out a gain correction operation by constantly adjusting a gain coefficient of an output characteristic curve of ADC until a gain error is less than 2 LSB, and then going to Step 4; Step 4: carrying out a final result operation by carrying out a weighted addition by sampling an optimal weight on individual bits of the first original binary value to obtain a summed value, which is then multiplied by a gain factor; after the final result operation, giving out a data result from a “bincode” port of the control module, and outputting a high pulse signal of one cycle from a port of control module (“eoc” port).