Liquid crystal display having contact holes adjacently disposed in thin film transistor forming region

摘要

A liquid crystal display includes: a first substrate; a gate line and a common voltage line that are on the first substrate; a gate insulating layer on the gate line and the common voltage line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode that are on the semiconductor layer; a pixel electrode on the data line and the drain electrode; a passivation layer on the pixel electrode; a common electrode on the passivation layer; a second substrate; and a liquid crystal layer interposed between the first and second substrates. The pixel electrode contacts the drain electrode via a first contact hole, the common electrode contacts the common voltage line via a second contact hole in the gate insulating layer and the passivation layer, and the first and second contact holes are adjacently disposed in a thin film transistor forming region.

主权项

1. A liquid crystal display comprising:
a first substrate; a gate line and a common voltage line that are on the first substrate; a gate insulating layer on the gate line and the common voltage line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode that are on the semiconductor layer; a pixel electrode on the data line and the drain electrode; a passivation layer on the pixel electrode, the pixel electrode being between the first substrate and the passivation layer; a common electrode on the passivation layer; a second substrate; and a liquid crystal layer interposed between the first and second substrates, wherein the pixel electrode contacts the drain electrode via a first contact hole, the common electrode contacts the common voltage line via a second contact hole in the gate insulating layer and the passivation layer, and the first and second contact holes are adjacently disposed in a thin film transistor forming region, wherein the common voltage line includes a horizontal portion traversing a middle of the pixel electrode, and a vertical portion vertically extending along the data line, one end of the vertical portion of the common voltage line is provided with a common voltage line extension, wherein the gate line includes a first gate electrode and a second gate electrode, the second gate electrode is not provided in a region where the common voltage line extension is disposed, and the common voltage line extension and the first gate electrode are adjacently disposed in an extending direction of the gate line.