High speed transceiver

摘要

Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.

主权项

1. A communication transceiver device comprising:
a host interface including at least two inputs for receiving signals from a host device at a total data rate of at least 40 Gbit/s; host-side analog-to-digital converter (ADC) circuitry configured to digitize the received signals to generate at least two digital data channels each having a first data rate; a digital signal processor configured to digitally condition the at least two digital data channels and multi-level encode the at least two digital data channels to generate a reduced number of one or more multiplexed digital data channels that each have a second data rate higher than the first data rate; line-side digital-to-analog converter (DAC) circuitry configured to convert the multiplexed one or more digital data channels into one or more differential output signals including a first differential output signal, wherein the line-side DAC circuitry comprises a first DAC and a second DAC; a line interface comprising one or more differential outputs each configured to transmit a corresponding one of the differential output signals onto corresponding paired differential cables of a communication link, wherein the line-side DAC circuitry is configured to deliver the one or more differential output signals onto the paired differential cables such that the line interface operates at a total data rate of at least 40 Gbit/s, wherein the first DAC and the second DAC are configured to deliver the first differential output signal; and skew adjustment circuitry configured to receive a skew indication signal over the communication link and to generate one or more skew control signals operable to provide skew adjustment to the first DAC and the second DAC, wherein during a start-up phase of the communication link the skew adjustment circuitry is configured to adjust a value of the one or more skew control signals and to observe a corresponding change to a value of the skew indication signal.