发明名称 Circuit for mixed memory storage and polymorphic logic computing
摘要 A circuit utilizing memcapacitive elements for mixed memory storage and polymorphic computing is introduced. The circuit includes a plurality of memory cells each selectively or fixedly connected to a word line, bit line and dual bit line. Each memory cell includes a memcapacitive element. Voltage pulse generators can selectively applying voltage pulses to the memory cells. A method for mixed memory storage and polymorphic computing in at least two memory cells is provided. Data is stored by selectively applying voltage pulses to an individual memory cell to set an internal charge level of the memcapacitive element. Logic functions are conducted by applying voltage pulses having independent amplitudes to at least two memory cells to achieve internal charges in the memcapacitive elements of the cells to store an output bit according to a logic map that depends upon applied independent voltage pulse amplitudes.
申请公布号 US9570140(B2) 申请公布日期 2017.02.14
申请号 US201414770718 申请日期 2014.03.07
申请人 The Regents of the University of California 发明人 Di Ventra Massimiliano;Traversa Fabio Lorenzo;Pershin Yuriy V.
分类号 G11C11/24;G11C11/4091;G11C11/406;H01L49/02;G11C11/401;G11C7/10;G11C11/404;H01L21/28 主分类号 G11C11/24
代理机构 Greer, Burns & Crain, Ltd. 代理人 Greer, Burns & Crain, Ltd. ;Fallon Steven P.
主权项 1. A circuit for mixed memory storage and polymorphic computing, comprising: a plurality of memory cells each selectively or fixedly connected to a word line, bit line and dual bit line, wherein each memory cell includes a memcapacitive element; voltage pulse generators for selectively applying voltage pulses the memory cells; and control circuitry apply to control the voltage pulse generators conduct at least one logic operation using two or more of the memory cells, wherein the at least one logic operation is performed according to a logic map providing logic necessary for computation.
地址 Oakland CA US