PMOS gate driving circuit

摘要

The present invention provides a PMOS gate driving circuit, comprising a plurality of GOA unit circuits which are cascade connected, and the GOA unit circuit of every stage comprises a pull-up controlling module (100), a pull-up module (200), a transmission module (300), a first pull-down module (400), a bootstrap capacitor (500) and a pull-down holding module (600); the pull-up controlling module (100) receives a constant negative voltage level (VSS1), which can reduce the influence of PMOS element leakage to the first node (Q(N)); the pull-down holding module (600) is provided with a dual inverter (F1) comprising P-type thin film transistors, and utilizes special leakage prevention design, which can reduce the leakage of the first node (Q(N)) to prevent the influence of the electrical property of the depletion-mode P-type thin film transistors to the output of the inverter, raise the stability of the gate driving circuit, and promote the integration of the panel. The frame width of the liquid crystal display panel can be decreased in advance, particularly to be suitable for small size panel which requires higher demands to the frame width.

主权项

1. A PMOS gate driving circuit, comprising a plurality of gate driver on array (GOA) unit circuits which are cascade connected, and the GOA unit circuit of every stage comprises a pull-up controlling module, a pull-up module, a transmission module, a first pull-down module, a bootstrap capacitor and a pull-down holding module;
N is set to be a positive integer, and in the GOA unit circuit of the Nth stage: the pull-up controlling module is electrically coupled to a first node and the pull-down holding module; the pull-up controlling module at least comprises a P type thin film transistor, and at least receives a stage transfer signal of the GOA unit circuit of the former N−1th stage and a constant negative voltage level; the pull-up module comprises: a twenty-second P-type thin film transistor, and a gate of the twenty-second P-type thin film transistor is electrically coupled to the first node, and a source is electrically coupled to an Mth clock signal, and a drain is electrically coupled to a scan driving signal; the transmission module comprises: a twenty-first P-type thin film transistor, and a gate of the twenty-first P-type thin film transistor is electrically coupled to the first node, and a source is electrically coupled to the Mth clock signal, and a drain is electrically coupled to the stage transfer signal; the first pull-down module is electrically coupled to the first node and the scan driving signal, and comprises a fortieth P-type thin film transistor and a forty-first P-type thin film transistor which are mutually cascade connected, and employed to pull up a voltage level of the first node to a voltage level of the scan driving signal in a non-functioning period; one end of the bootstrap capacitor is electrically coupled to the first node, and the other end is electrically coupled to the scan driving signal; the pull-down holding module comprises: an inverter comprising a plurality of P-type thin film transistor, and an input end of the inverter is electrically coupled to the first node, and an output end is electrically coupled to a second node; a thirty-second P-type thin film transistor, and a gate of the thirty-second P-type thin film transistor is electrically coupled to the second node, and a source is electrically coupled to a drain of the forty-first P-type thin film transistor, and a drain is electrically coupled to a first constant positive voltage level; a forty-second P-type thin film transistor, and a gate of the forty-second P-type thin film transistor is electrically coupled to the second node, and a drain is electrically coupled to the first node, and a source is electrically coupled to a drain of an eighty-second P-type thin film transistor; the eighty-second P-type thin film transistor, and a gate of the eighty-second P-type thin film transistor is electrically coupled to the first node, and a source is electrically coupled to the constant negative voltage level, and the drain is electrically coupled to a drain of an eighty-first P-type thin film transistor; the eighty-first P-type thin film transistor, and a gate of the eighty-first P-type thin film transistor is electrically couple to the second node, and a source is electrically couple to a second constant positive voltage level, and the drain is electrically couple to the drain of the eighty-second P-type thin film transistor; the first constant positive voltage level is lower than the second constant positive voltage level.