主权项 |
1. A delay locked loop, comprising:
a programmable delay line, receiving an input signal to generate a first internal signal and an output signal, the output signal and the first internal signal having different phases; a control logic, receiving the output signal and accordingly providing a selection signal; a selection circuit, coupled to the control logic, selectively providing a reference clock signal or the output signal as the input signal; and a mask, coupled to the selection circuit, the control logic and the delay line, controlled by the first internal signal and the selection signal to determine whether to utilize the reference clock signal as the input signal. |