发明名称 DELAY LOCKED LOOP AND ASSOCIATED CONTROL METHOD
摘要 A control method for a delay locked loop includes: delaying an input signal to generate an internal signal; delaying the internal signal to generate an output signal; and selectively providing a reference clock signal or the output signal as the input signal according to the output signal and the internal signal.
申请公布号 US2017041009(A1) 申请公布日期 2017.02.09
申请号 US201514956554 申请日期 2015.12.02
申请人 MStar Semiconductor, Inc. 发明人 Weng Meng-Tse;Liu Hsian-Feng;Lee Chieh-Wen
分类号 H03L7/08;H03K5/14 主分类号 H03L7/08
代理机构 代理人
主权项 1. A delay locked loop, comprising: a programmable delay line, receiving an input signal to generate a first internal signal and an output signal, the output signal and the first internal signal having different phases; a control logic, receiving the output signal and accordingly providing a selection signal; a selection circuit, coupled to the control logic, selectively providing a reference clock signal or the output signal as the input signal; and a mask, coupled to the selection circuit, the control logic and the delay line, controlled by the first internal signal and the selection signal to determine whether to utilize the reference clock signal as the input signal.
地址 Hsinchu Hsien TW