DATA PROCESSING SYSTEM

摘要

The present invention easily realizes synchronization between processor cores in a multicore system. A data processing system receiving a group of data of different kinds from the outside and performing data processes by kinds includes: a plurality of data process control units corresponding to the kinds of the data group and performing data processes on the data group of corresponding kinds; and a memory unit which can be accessed by the data process control units and has a first region storing a value indicating whether the data process by the data process control units can be executed or not. Each of the data process control units updates the value in the first region on completion of preparation for executing the data process of itself and, when the value in the first region becomes a predetermined value, synchronizes start timings of the data processes and executes the data processes.

主权项

1. A data processing system for receiving contents including
a first data stream and a second data stream, processing data of contents and outputting results of data process, comprising: a first processor configured to process data of the first data stream; a second processor configured to process data of the second data stream; a memory configured to be accessed by the first processor and the second processor and, having a first information storing a value controlling execution of data process; a first output configured to output a result of data process of the first data stream; and a second output configured to output a result of data process of the second data stream, wherein each of the first processor and the second processor updates the first information on completion of preparation for executing the data process of itself and, wherein the first processor and the second processor start their data process when the first information becomes a predetermined value,the first processor further comprising:
a first reference clock generation unit configured to generate a first reference time expressing lapse time since start of the data process based on a first operation clock supplied to itself; and a first controller configured to update the first information and to store the first reference time in the memory,the second processor further comprising:
a second reference clock generator configured to generate a second reference time expressing lapse time since start of the data process based on a second operation clock supplied to itself; and a second controller configured to update the first information and to store the second reference time in the memory, wherein the first controller is configured to start the first reference clock generator on confirmation that the first information becomes the predetermined value, wherein the second controller is configured to start the second reference clock generator on confirmation that the first information becomes the predetermined value.