| 摘要 |
To provide a small driver IC, a driver IC with a narrow width, a driver IC capable of high-speed operation, a small semiconductor device, a semiconductor device with a narrow width, or a semiconductor device capable of high-speed operation. The semiconductor device includes first to third circuits. The first and second circuits each include transistors with a first channel width. The third circuit includes transistors with a second channel width. The second channel width is larger than the first channel width. The first circuit is configured to select one of first to 2N-th potentials (N is an integer of 1 or more). The second circuit is configured to select one of (2N+1)-th to 4N-th potentials. The third circuit is configured to select the potential selected by the first circuit or the potential selected by the second circuit. The first to third circuits are arranged in line. |
| 主权项 |
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein a gate of the first transistor and a gate of the third transistor are electrically connected to a first wiring, wherein a gate of the second transistor and a gate of the fourth transistor are electrically connected to a second wiring, wherein a gate of the fifth transistor is electrically connected to a third wiring, wherein a gate of the sixth transistor is electrically connected to a fourth wiring, wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor, wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, wherein the first transistor, the third transistor, and the fifth transistor are arranged in line, and wherein a channel region of the fifth transistor is located between a channel region of the first transistor and a channel region of the third transistor. |
