Reduced Local Threshold Voltage Variation MOSFET Using Multiple Layers of Epi for Improved Device Operation

摘要

A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement. Mixed epitaxial layer growth materials inducing tensile or compressive gate stresses can be advantageously used with the invention to further improve device characteristics.

主权项

1. A transistor device structure, enabled for providing reduced variability of threshold voltage induced by random dopant induced threshold voltage variations (sigma-Vt) and reduced short channel effects, the structure comprising:
a lightly doped substrate; a gate structure having a conductive gate electrode over lying a gate dielectric on the substrate and having its side walls covered by a protective dielectric; a channel in the substrate, under the conductive gate electrode under the gate dielectric; a source spaced away from the gate on a first side, but connected to the channel under the gate by a source extension that abuts the gate structure but is insulated from the gate electrode by the protective dielectric on the side walls of the gate electrode; a drain spaced away from the gate on a second side opposite the first side, but connected to the channel under the gate by a drain extension that is insulated from the gate electrode by the protective dielectric on the side walls of the gate electrode; wherein each of the source and drain comprise a plurality of heavily doped layers of semiconducting material, deposited on substrate using low temperature deposition process; wherein the source extension is a doped layer of deposited semiconducting material deposited on the substrate using a low temperature deposition process that has a temperature of 650 degrees centigrade or less; wherein the drain extension is a doped layer of deposited semiconducting material deposited on the substrate using low temperature deposition process; and wherein the interfaces between the gate dielectric and the substrate, the source extension and the substrate and between, the drain extension and the substrate are all coplanar on the substrate surface.