| 摘要 |
A processor chip, a layout method, and a method of accessing data. The processor chip comprises processor core (200) sets, a last level cache (LLC) module, and a network composed of a router module (230), the LLC module comprising tag memory units (210) and data memory units (220), the tag memory units being located on a first position of the processor chip, the processor core sets being located on a second position of the processor chip, the first position being located on the center of the second position; the data memory units being located on a third position of the processor chip, the third position being located around the second position. A first processor core of a processor core set accesses, according to a data access request, a tag memory unit, obtaining the tag that the data access request corresponds to, and accesses a data memory unit according to the tag, obtaining the data to be accessed. The described technical solutions are conducive to relieve congestion caused when the processor core set accesses the LLC module, improving execution efficiency of the access request. |
