发明名称 |
REDUCING TRANSMITTER ENCODING JITTER IN A C-PHY INTERFACE USING MULTIPLE CLOCK PHASES TO LAUNCH SYMBOLS |
摘要 |
Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. One method includes providing a plurality of launch clock signals, including launch clock signals having a different phase shifts, determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols, and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-phase interface. Selecting one of the plurality of launch clock signals may include selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, and selecting a second launch clock signal when the transition in signaling state begins at an undriven state. An edge in the first launch clock signal may occur before a corresponding edge in the second launch clock signal. |
申请公布号 |
US2017039163(A1) |
申请公布日期 |
2017.02.09 |
申请号 |
US201615332756 |
申请日期 |
2016.10.24 |
申请人 |
QUALCOMM Incorporated |
发明人 |
Sejpal Dhaval;Chou Shih-Wei;Lee Chulkyu;Kwon Ohjoon;Wiley George Alan |
分类号 |
G06F13/42 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
1. A method of transmitting data on a multi-wire interface, comprising:
providing a plurality of launch clock signals, certain of the launch clock signals having a different phase-shift with respect to a symbol clock used to control symbol transmission on a 3-wire interface, wherein during each symbol transmission, a 3-phase signal is transmitted on each wire of the 3-wire interface, the 3-phase signal transmitted on each wire being out-of-phase with signals transmitted on each other wire of the 3-wire interface; determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols; and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-wire interface, wherein selecting one of the plurality of launch clock signals includes:
selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, andselecting a second launch clock signal when the transition in signaling state begins at an undriven state, and wherein an edge in the first launch clock signal occurs before a corresponding edge in the second launch clock signal. |
地址 |
San Diego CA US |