| 摘要 |
A drive circuit (1) and a shift register circuit (10). The drive circuit (1) comprises multiple shift register circuits (10) that are disposed in a cascading mode. Each shift register circuit (10) comprises a transmission-gate lock circuit (11) and a signal transmission circuit (12). The transmission-gate lock circuit (11) comprises a transmission gate (112). A first clock signal (13) triggers the transmission gate (112), so that a previous second level transmission signal (Qn-2) is output to the signal transmission circuit (12) through the transmission gate (112) to form a current level transmission signal (Qn). A second clock signal (14) controls the current level transmission signal (Qn) to generate a current level gate driver signal (Gn) by using the signal transmission circuit (12). By means of the foregoing manner, the drive circuit (1) can be applicable to a CMOS process, and has low power consumption and a wide noise margin. |
