发明名称 HYBRID SUBTRACTIVE ETCH/METAL FILL PROCESS FOR FABRICATING INTERCONNECTS
摘要 In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.
申请公布号 US2017040213(A1) 申请公布日期 2017.02.09
申请号 US201615157891 申请日期 2016.05.18
申请人 International Business Machines Corporation 发明人 Bruce Robert L.;Fritz Gregory M.;Joseph Eric A.;Miyazoe Hiroyuki
分类号 H01L21/768;H01L21/288;H01L21/285;H01L23/522;H01L23/532;H01L21/3213;H01L23/528 主分类号 H01L21/768
代理机构 代理人
主权项
地址 Armonk NY US