发明名称 記憶装置
摘要 A storage device in which held voltage is prevented from decreasing due to feedthrough in writing data to the storage device at high voltage is provided. The storage device includes a write circuit, a bit line, a word line, a transistor, and a capacitor. A gate of the transistor is electrically connected to the word line. One of a source and a drain of the transistor is electrically connected to the bit line. The other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor. The other terminal of the capacitor is electrically connected to a ground. The write circuit includes an element holding write voltage and a circuit gradually decreasing voltage from the element holding write voltage. The write voltage is output from the write circuit to the word line.
申请公布号 JP6077927(B2) 申请公布日期 2017.02.08
申请号 JP20130102028 申请日期 2013.05.14
申请人 株式会社半導体エネルギー研究所 发明人 塩野入 豊;井上 聖子
分类号 G11C11/407;G11C11/405;H01L21/8242;H01L27/108;H01L29/786 主分类号 G11C11/407
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