| 摘要 |
An analog-to-digital converter (ADC) is provided. The ADC includes a plurality of pipelined ADCs and an adjustment circuit. Each pipelined ADC is adapted to receive an analog input signal, has an adjustable transfer function, and includes a compensator. The adjustment circuit is coupled to each pipelined ADC to be able to adjust the transfer function for each pipelined ADC so as to generally eliminate an estimation ambiguity. Additionally, the adjustment circuit estimates an inter-stage error that includes at least one of an inter-stage gain error and a DAC gain error and adjusts the compensator for each pipelined ADC to compensate for the inter-stage error. |
