发明名称 演算処理装置及び演算処理方法
摘要 An processor includes: multiple arithmetic processing sections to execute arithmetic processing; and multiple registers provided for the multiple arithmetic processing sections. A register value of a register of the multiple registers corresponding to a given one of the multiple arithmetic processing sections is changed if program execution by the given one of the multiple arithmetic processing sections reaches a predetermined location in a program, and priorities of the arithmetic processing sections are dynamically determined in response to register values of the registers.
申请公布号 JP6074932(B2) 申请公布日期 2017.02.08
申请号 JP20120160696 申请日期 2012.07.19
申请人 富士通株式会社 发明人 近藤 祐史
分类号 G06F9/52;G06F9/30;G06F9/50;G06F15/167;G06F15/173 主分类号 G06F9/52
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