发明名称 半導体装置、半導体装置の制御方法
摘要 PROBLEM TO BE SOLVED: To reduce malfunction.SOLUTION: A memory cell MC00 includes a fuse element EF connected between a node N11 of a bit line pair BL0 and a node N12 of an inverted bit line xBL0. An intermediate region of the fuse element EF is connected to a node N13 of a word line WL0. Thus, the fuse element EF electrically includes a first fuse element F1 connected between the bit line BL0 and the word line WL0, and a second fuse element F2 connected between the inverted bit line xBL0 and the word line WL0. A voltage application circuit 21 connected to the bit line pairs BL0, xBL0 causes an imbalance between the ohmic values of the first fuse element F1 and the second fuse element F2. The memory cell MC00 stores the state of input data DI0 by imbalance of the ohmic values of the first fuse element F1 and the second fuse element F2 that are included in the fuse element EF.
申请公布号 JP6075105(B2) 申请公布日期 2017.02.08
申请号 JP20130026687 申请日期 2013.02.14
申请人 株式会社ソシオネクスト 发明人 小牧 正樹
分类号 G11C17/14 主分类号 G11C17/14
代理机构 代理人
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