Error correction code decoder with stochastic floor mitigation

摘要

A method and apparatus as described herein provide a novel modification to any iterative FEC decoder method that can improve FER performance in the error floor region. Many iterative FEC methods, such as commonly used LDPC decoders, have error floors where the performance of the decoder does not improve below a certain threshold. Error Floors are caused by trapping sets from which traditional methods cannot escape. With Stochastic Floor Mitigation, according to embodiments of the present disclosure, noise is strategically added to the operations occurring during decoding resulting in significantly improved error floor performance.

主权项

1. An Error Correction Code (ECC) decoder, comprising:
one or more layer processors, each of the one or more layer processors including
a check node processor;a delay element for storing extrinsic information; anda stochastic floor mitigation (SFM) circuit configured to correct trapping set conditions, the stochastic floor mitigation circuit comprising a noise generator circuit provided between a check node processor output and an output of the ECC decoder.