Circuitry and method for timing speculation via toggling functional critical paths

摘要

Toggling functional critical path timing sensors measure delays in toggling functional critical paths that are replicas of actual critical paths or representations of worst-case delay paths. A Toggle flip-flop or Linear-Feedback-Shift Register (LFSR) drives high-transition-density test patterns to the toggling functional critical paths. When a toggling functional critical path's delay fails to meet set-up timing requirement to a next register, the toggling functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. A margin delay buffer adds a delay to the toggling functional critical path before being clocked into an early capture flip-flop. A reference register receives the test pattern without the delay of the toggling functional critical path, and an exclusive-OR (XOR) gate compares outputs of reference and early capture flip-flops to generate timing failure signals to the controller.

主权项

1. A timing-failure-predicting integrated circuit comprising:
a toggling pattern generator that generates a toggle pattern having a high density of transitions; a plurality of toggling functional critical paths that receives the toggle pattern generated by the toggling pattern generator; a plurality of toggling functional critical path timing sensors, each receiving an output of a toggling functional critical path in the plurality of toggling functional critical paths; a plurality of fail signals generated by the plurality of toggling functional critical path timing sensors, wherein a fail signal is generated when a delay through a toggling functional critical path exceeds a timing requirement; and a VDD adjustment controller that receives the fail signals generated by the plurality of toggling functional critical path timing sensors, the VDD adjustment controller causing a power-supply voltage to the plurality of toggling functional critical paths and to the plurality of toggling functional critical path timing sensors to be increased when the fail signal is received, the VDD adjustment controller causing the power-supply voltage to be reduced when no fail signal is received for a period of time, wherein the power-supply voltage is adjusted to compensate for timing failures detected through the toggling functional critical paths.