FinFETs with reduced parasitic capacitance and methods of forming the same

摘要

An integrated circuit structure includes a semiconductor substrate, a semiconductor strip over a portion of the semiconductor substrate, and a Shallow Trench Isolation (STI) region on a side of the semiconductor strip. The STI region includes a dielectric layer, which includes a sidewall portion on a sidewall of the semiconductor strip and a bottom portion. The dielectric layer has a first etching rate when etched using a diluted HF solution. The STI region further includes a dielectric region over the bottom portion of the dielectric layer. The dielectric region has an edge contacting an edge of the sidewall portion of the dielectric layer. The dielectric region has a second etching rate when etched using the diluted HF solution, wherein the second etching rate is smaller than the first etching rate.

主权项

1. An integrated circuit structure comprising:
a semiconductor substrate; a semiconductor strip over a portion of the semiconductor substrate; a Shallow Trench Isolation (STI) region on a side of the semiconductor strip, wherein the STI region comprises:
a dielectric layer comprising:
a sidewall portion on a sidewall of the semiconductor strip; anda bottom portion;a dielectric region over the bottom portion of the dielectric layer, wherein the dielectric region comprises an edge contacting an edge of the sidewall portion of the dielectric layer, wherein a top surface of the sidewall portion of the dielectric layer comprises a middle portion, and a first portion and a second portion on opposite sides of, and joined to, the middle portion, with the middle portion being lower than the first portion and the second portion;a liner oxide comprising a sidewall portion between, and in contact with, a sidewall of the semiconductor strip and a sidewall of the sidewall portion of the dielectric layer; and a gate dielectric layer contacting a sidewall of the semiconductor strip.