发明名称 Semiconductor device and process
摘要 A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive material is deposited and the conductive material is patterned into a conductive line and a via. A dielectric material is deposited over the conductive line and the via, and the dielectric material and the via are planarized.
申请公布号 US9564396(B2) 申请公布日期 2017.02.07
申请号 US201414498529 申请日期 2014.09.26
申请人 Taiwan Semiconductor Manufucturing Company, Ltd. 发明人 Kao Hsiang-Lun;Lin Tien-Lu;Wang Yung-Chih;Liao Yu-Chieh
分类号 H01L23/522;H01L21/768;H01L23/532 主分类号 H01L23/522
代理机构 Slater Matsil, LLP 代理人 Slater Matsil, LLP
主权项 1. A semiconductor device comprising: a conductive line over a substrate, wherein the conductive line extends a first distance from the substrate; a via over the substrate, wherein a bottom surface of the via and a bottom surface of the conductive line are substantially planar, wherein the via comprises a first material that extends from the substrate a second distance larger than the first distance; a liner in physical contact with the conductive line, the via, and the substrate, wherein the liner continuously extends from the conductive line to the via, wherein the liner has a thickness of between about 50 Å to about 500 Å; and a dielectric over the conductive line and between the conductive line and the via, wherein the dielectric comprises a first material that extends throughout the dielectric.
地址 Hsin-Chu TW