| 主权项 |
1. A static random access memory (SRAM) chip comprising:
a plurality of SRAM cells, wherein each of the plurality of SRAM cells comprise:
a source voltage reference conductor;a first ground reference conductor;two cross-coupled inverters, andtwo pass-gate devices; and a plurality of cell current tracking cells, wherein each of the plurality of cell current tracking cells comprises:
a first half-cell, wherein the first half-cell comprises:
a first tracking bit-line conductor;a first complementary metal oxide semiconductor (CMOS) comprising:
a first pull down (PD) device, anda first pull up (PU) device, anda first pass-gate device configured to track a current; anda second half-cell, wherein the second half-cell comprises:
a second CMOS comprising:
a second PD device, anda second PU device, anda second pass-gate device configured to receive a word line signal; a plurality of capacitance tracking cells, wherein each of the capacitance tracking cells of the plurality of capacitance tracking cells comprise:
a third half-cell comprising:
a third pass-gate device configured to track a bit-line capacitance, anda third CMOS comprising:
a third PU device, anda third PD device having a source node configured to be electrically floating;wherein the first half-cell is different from the second half-cell;wherein a gate of the first PD device of the first CMOS or a gate of the first PU device of the first CMOS is electrically connected to the source voltage reference conductor;wherein a drain node of the second PU device is electrically isolated from a drain node of the second PD device;wherein a gate node of the first pass-gate device is electrically connected to a tracking enable conductor; andwherein a gate node of the second pass-gate device is electrically connected to a first word-line conductor. |
