发明名称 Circuitry and method for measuring negative bias temperature instability (NBTI) and hot carrier injection (HCI) aging effects using edge sensitive sampling
摘要 Toggling functional critical path timing sensors measure delays in toggling functional critical paths that continuously receive patterns from an aging pattern generator. Wear is accelerated. A margin delay adjustment controller sweeps margin delays until failures occur to measure delays. The margin delay is then adjusted in functional critical path timing sensors that add the margin delay to functional critical paths that carry user data or chip controls during normal operation. When the path delays fail to meet requirements, the functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. Wear on the toggling functional critical paths is accelerated using both toggle and low-transition-density patterns. Circuit aging is compensated for by increasing margin delays to timing sensors.
申请公布号 US9564884(B1) 申请公布日期 2017.02.07
申请号 US201514791444 申请日期 2015.07.04
申请人 Qualcomm Incorporated 发明人 Quinton Bradley;McClements Trent;Hughes Andrew;Taneja Sanjiv
分类号 G06F1/10;H03K5/13;H03K5/00 主分类号 G06F1/10
代理机构 Smith Tempel Blaha LLC 代理人 Smith Tempel Blaha LLC
主权项 1. A wear-sensing integrated circuit comprising: an aging pattern generator that generates a plurality of patterns to accelerate wear of transistors; a plurality of toggling functional critical paths that receive patterns generated by the aging pattern generator; a plurality of toggling functional critical path timing sensors, each receiving an output of a toggling functional critical path in the plurality of toggling functional critical paths; a plurality of fail signals generated by the plurality of toggling functional critical path timing sensors, wherein a fail signal is generated when a delay through a toggling functional critical path exceeds a timing requirement; and a margin delay adjustment controller that receives the fail signals generated by the plurality of toggling functional critical path timing sensors, the margin delay adjustment controller adjusting a margin value in response to receiving the fail signals; wherein the margin value increases over time as the wear-sensing integrated circuit ages during a lifetime of the wear-sensing integrated circuit.
地址 San Diego CA US