Non-volatile static random access memory using a 7T1R cell with initialization and pulse overwrite

摘要

A non-volatile SRAM cell comprises a first inverter, a second inverter, a first access transistor, a second access transistor, and a variable resistive element. The first inverter voltage is supplied by a first differential supply. The second inverter voltage is supplied by a second differential supply. The variable resistive element coupling with a third access transistor in series is coupled to the first output node. The non-volatile SRAM cell operates in a restore operation comprising a dual supply initialization phase and a pulse-overwrite phase. During the dual supply initialization phase, the first differential supply increases before the second differential supply so as to initialize the first output node to a logic state. During the pulse-overwrite phase, the third access transistor is turned on for a switch period in order to discharge/charge the first output node.

主权项

1. A non-volatile static random access memory cell, comprising:
a first inverter, having a first input node and a first output node, voltage supplied by a first differential supply, wherein the first inverter comprises:
a first pull-up transistor having a source terminal coupled to a first high voltage;a first pull-down transistor having a source terminal coupled to a first low voltage, the first pull-down transistor having a drain terminal coupled to a drain terminal of the first pull-up transistor to form the first output node, wherein the difference between the first high voltage and the first low voltage is the first differential supply; a second inverter, having a second input node and a second output node, voltage supplied by a second differential supply, wherein the first input node is coupled to the second output node, the second input node is coupled to the first output node, wherein the second inverter comprises:
a second pull-up transistor having a source terminal coupled to a second high supply voltage;a second pull-down transistor having a source terminal coupled to a second low voltage supply, the second pull-down transistor having a drain terminal coupled to a drain terminal of the second pull-up transistor to form the second output node, wherein the difference between the second high voltage and the second low voltage is the second differential supply; a first access transistor having a gate terminal coupled to a first word line, the first access transistor having a source terminal coupled to the first output node; a second access transistor having a gate terminal coupled to the first word line, the second access transistor having a source terminal coupled to the second output node; and a variable resistive element coupling with a third access transistor in series, directly coupled between the first output node and the second output node; wherein the non-volatile static random access memory cell operates in a restore operation comprising a dual supply initialization phase and a pulse-overwrite phase, during the dual supply initialization phase the first high voltage raises before the second high voltage while the first low voltage is the same as the second low voltage and the first output node is initialized as logic “1”, during the pulse-overwrite phase the third access transistor is turned on for a switch period in order to discharge the first output node.