Deep-sleep wake up for a memory device

摘要

A memory device comprises memory banks, power gates, and bank wake-up circuits. Each of the memory banks has a core voltage supply. The power gates are coupled to the memory banks for charging the core voltage supplies and have a plurality of powering modes. The bank wake-up circuits are coupled to the power gates for selecting one of the plurality of power modes for charging the memory banks during a wake-up mode. The bank wake-up circuits sense the core voltage supplies during the wake-up mode. The bank wake-up circuits serially charge the memory banks as a function of the sensed core voltage supplies of the memory banks.

主权项

1. A memory device, comprising:
memory banks, wherein each of the memory banks has a core voltage supply; power gates coupled to the memory banks for charging the core voltage supplies, wherein the power gates have a plurality of powering modes; and bank wake-up circuits coupled to the power gates for selecting one of the plurality of power modes for charging the memory banks during a wake-up mode, wherein the bank wake-up circuits sense the core voltage supplies during the wake-up mode, and wherein the bank wake-up circuits serially charge the memory banks as a function of the sensed core voltage supplies of the memory banks.