Independent sense amplifier addressing and quota sharing in non-volatile memory

摘要

Independent sense amplifier addressing provides separate column addresses to individual sense amplifier groups within a single bay during one column address cycle. A memory system determines whether the individual memory cells or bits of a column at a bay can be skipped. For each sense amplifier group having at least one memory cell (or bit) that needs to be programmed, the system determines for the first column address whether the memory cell can be skipped. If a bit or memory cell having a first column address from the sense amplifier group can be skipped, the system determines a next bit having a column address from the group that needs to be programmed. The system groups the next column address for programming during the first column address cycle. The system can program a different column address for different sense amplifier groups within the bay during a single column address cycle.

主权项

1. A non-volatile memory system, comprising:
a bay of non-volatile storage elements configured for programming in a plurality of column address cycles, wherein the bay includes a first group of non-volatile storage elements associated with a plurality of columns and a second group of non-volatile storage elements associated with the plurality of columns; a first sense amplifier circuit associated with the first group of non-volatile storage elements of the bay, wherein the first sense amplifier circuit is configured to program in a first column address cycle a second non-volatile storage element of the first group having a second column address in response to determining that the second non-volatile storage element should be programmed and a first non-volatile storage element of the first group having a first column address can be skipped; and a second sense amplifier circuit associated with the second group of non-volatile storage elements of the bay, wherein the second sense amplifier circuit is configured to program in the first column address cycle a first non-volatile storage element of the second group having the first column address in response to determining that the first non-volatile storage element of the second group should be programmed.