| 发明名称 | Instruction and logic for flush-on-fail operation | ||
| 摘要 | A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation. | ||
| 申请公布号 | US9563557(B2) | 申请公布日期 | 2017.02.07 |
| 申请号 | US201414580632 | 申请日期 | 2014.12.23 |
| 申请人 | Intel Corporation | 发明人 | Kumar Sanjay;Sankaran Rajesh M.;Dulloor Subramanya R.;Anderson Andrew V. |
| 分类号 | G06F12/00;G06F13/00;G06F12/08 | 主分类号 | G06F12/00 |
| 代理机构 | Baker Botts L.L.P. | 代理人 | Baker Botts L.L.P. |
| 主权项 | 1. A processor, comprising: a front end including a decoder, the decoder including a first logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction; and a memory management unit (MMU) including: a second logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction; anda third logic to flush the dirty data from the volatile cache upon a subsequent FoF operation. | ||
| 地址 | Santa Clara CA US | ||