Method and circuit for delay adjustment monotonicity in a delay line

摘要

A delay circuit device configured for delay adjustment monotonicity and method of operating therefor. This delay circuit device is configured with hybrid coarse-fine delay cells and uses a sequence of these delay cells activated in a way that builds-up the delay as a sequence of fine steps until it reaches the coarse delay value. This configuration allows for the continuing build of propagation delay by adding the fine steps of the following delay cells. In this manner, the monotonicity of the signal delay circuit is ensured by the architecture independent from device mismatch, thus eliminating problems with conventional delay circuits such as gaps and overlaps specific the these conventional delay cells.

主权项

1. A delay circuit device comprising:
a plurality of delay stages having a delay circuit input, a delay circuit output, and a delay code input, each of the delay stages including:
a first delay cell having a first delay input and a first delay output;a second delay cell having a second delay input and a second delay output;a third delay cell having a third delay input and a third delay output;wherein the first delay input is electrically coupled to a first input node;wherein the first delay output and the second delay input are electrically coupled to a first joint node, the third delay input is electrically coupled to a second input node, wherein second delay output and the third delay output are electrically coupled to a second joint node; andwherein each of the first, second, and third delay cells is a hybrid coarse-fine delay cell that includes a signal strength level configured by the delay code input to produce a propagation delay for an input signal that ranges from zero delay to a coarse delay amount with incremental fine delay amounts; wherein the plurality of delay stages are configured in a series connection wherein the first delay stage in the series connection has the first input node configured to the delay circuit input and the second joint node configured to the delay circuit output; and wherein each delay stage is configured such that the first joint node of the delay stage is electrically coupled to the first input node of an adjacent delay stage and the second input node of the delay stage is electrically coupled to the second joint node of the adjacent delay stage.