Impedance-based flow control for a two-wire interface system with variable frame length

摘要

A two wire interface is disclosed that serializes messaging signals and GPIO signals into frames transmitted over a transmit pin. The two wire interface is configured to perform flow control by monitoring a voltage for the transmit pin.

主权项

1. An integrated circuit, comprising:
a first processor; a transmit pin; a GPIO interface configured to receive a transmit set of GPIO signals from the processor and to transmit a first portion of the transmit set over a plurality of GPIO pins to a remote second processor; a finite state machine configured to serialize a remaining second portion of the transmit set of GPIO signals from the GPIO interface into a first virtual GPIO (VGI) frame and a second VGI frame, wherein the first VGI frame and the second VGI frame each ends with a stop bit; a transmit buffer configured to transmit an initial portion of the first VGI frame's stop bit over the transmit pin through a low output impedance responsive to at least one cycle of an oversampling clock signal and to transmit a remaining portion of first VGI frame's stop bit through a high output impedance responsive to a plurality of cycles of the oversampling clock signal; and a transmit control circuit configured to command the transmit buffer to transmit an initial portion of the second VGI frame responsive to a determination that a voltage for the transmit pin was above a threshold voltage during the transmission of the remaining portion of the first VGI frame's stop bit.