Dynamic clock regulation based on duty cycle thresholds

摘要

A clock frequency is controlled by determining a cumulative duty cycle according to a ratio of a cumulative time, during an interval, that the clock frequency has a frequency greater than or equal to a design frequency threshold value to a duration of the interval. A frequency of the clock frequency is controlled to be a first frequency value when the cumulative duty cycle is less than a first duty cycle threshold; and controlled to be a second frequency value substantially less than the first frequency value when the cumulative duty cycle is greater than a second duty cycle threshold. The second duty cycle threshold is greater than or equal to the first duty cycle threshold.

主权项

1. A computer-implemented method for controlling a clock frequency, the computer-implemented method comprising:
determining a cumulative duty cycle (DC) according to a ratio of a cumulative time, during an interval, that the clock frequency has a frequency greater than or equal to a design frequency threshold value to a duration of the interval; controlling a frequency of the clock frequency to be a first frequency value when the cumulative DC is less than a first duty cycle threshold (DCT); and controlling the frequency of the clock frequency to be a second frequency value less than the first frequency value when the cumulative DC is greater than a second DCT, wherein the second DCT is greater than or equal to the first DCT, and wherein the design frequency threshold value is a maximum design frequency of a circuit operated using a signal having the clock frequency or a predetermined fraction of the maximum design frequency.