Semiconductor device

摘要

Embodiments of the present invention relate to a latch circuit (L20) which latches a data mask signal (DM) in response to a one-shot signal (NS), and changes the data mask signal (DM) to an active level in response to an error signal (ERR), which indicates that an error is present in write data (DQ), being at an active level; a buffer circuit (BF2) which outputs the data mask signal (DM) that has been latched by the latch circuit (L20), said data mask signal (DM) being output in response to a write clock signal (WCLK2); and a main amplifier (80) which outputs the write data (DQ) to an internal circuit on the condition that the data mask signal (DM) which has been output from the buffer circuit (BF2) is at an inactive level. The present invention can prevent the writing of erroneous write data, and is capable of preventing increased chip surface area.

主权项

1. A semiconductor device comprising:
a verification circuit that sets an error signal to an active level in response to the presence of an error in write data comprising a plurality of bits; a latch circuit that latches a data mask signal in response to a first timing signal and changes said latched data mask signal to an active level in response to said error signal being active-level; a buffer circuit that outputs said data mask signal that was latched in said latch circuit in response to a second timing signal; and a main amplifier that outputs said write data to an internal circuit under the condition that said data mask signal that was output from said buffer circuit is an inactive level; wherein said first timing signal is activated prior to actuation of said second timing signal, said second timing signal is activated after the level of said error signal has been established, and no other latch circuit that performs latching operation synchronized with at least said first timing signal is interposed between said latch circuit and said buffer circuit.