发明名称 Data processor and data processing method including a decision circuit that compares input pixel data to defective pixel data
摘要 A plurality of pieces of first input data are input to a first decision circuit in an order based on a first rule. The memory has a plurality of first memory areas that respectively store a plurality of pieces of first data that match at least part of the plurality of pieces of first input data. The first decision circuit compares the first data read from the memory with the first input data to be input. When they do not match each other, The first decision circuit compares the first data with the first input data to be input next. When they match, The first decision circuit compares the first data read next from the memory on the basis of the first read pointer incremented with the first input data to be input next.
申请公布号 US9565380(B2) 申请公布日期 2017.02.07
申请号 US201514659795 申请日期 2015.03.17
申请人 MegaChips Corporation 发明人 Kotani Manabu
分类号 H04N5/367;H04N1/32 主分类号 H04N5/367
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A data processor comprising: a memory that stores data; and a first decision circuit that decides whether data to be input matches data in the memory, wherein a plurality of pieces of first input data on pixels are input to the first decision circuit in an order based on a first rule, the memory has a plurality of first memory areas that respectively store a plurality of pieces of first data that match at least part of the plurality of pieces of first input data, the first decision circuit reads the plurality of pieces of first data from the memory in an order based on a second rule identical to the first rule, when addresses of the plurality of first memory areas are viewed in ascending order, the plurality of pieces of first data respectively stored in the plurality of first memory areas are arranged in an order to be read by the first decision circuit, the data processor further comprises a first read pointer that indicates an address of a first memory area being a read target among the plurality of first memory areas, the first decision circuit compares one of the pieces of first data read from the memory on the basis of the first read pointer with one of the pieces of first input data to be input, when the one piece of first data does not match the one piece of first input data, the first decision circuit compares the one piece of first data with another of the pieces of first input data to be input next, when the one piece of first data matches the one piece of first input data, the first decision circuit increments the first read pointer to a succeeding value and compares another of the pieces of first data read next from the memory on the basis of the first read pointer incremented with another of the pieces of first input data to be input next, the memory further comprising a plurality of second memory areas that respectively store a plurality of pieces of second data, and the data processor further comprising a second decision circuit that operates in parallel with the first decision circuit and decides whether second input data matches one of the pieces of second data.
地址 Osaka-shi JP