Active probe pod in logic analyzer

摘要

An active probe pod used in a logic analyzer is disclosed. The active probe pod may be connected to the logic analyzer having a FPGA decoder and to a DUT circuit board. The active probe pod may include a LVDS differential ire component connected to the FPGA decoder and a front-end circuit board for capturing a weak signal input from the DUT circuit board. The front-end circuit board is adapted not to transmit the captured weak signal input over a long-distance signal transmission path, which helps minimize interferences with the weak signal input, while outputting a LVDS differential signal to the FPGA decoder for decoding. As the front-end circuit board is used for capturing the weak signal input, which falls within the category of one short-distance signal transmission, the signal reflection may not take place, without affecting the signal quality and/or attenuating the signal strength.

主权项

1. An active probe pod used in a logic analyzer having a field-programmable gate array (FPGA) decoder, the active probe pod connected to the field-programmable gate array (FPGA) decoder and a device under test (DUT) circuit board, the active probe pod comprising:
a low-voltage differential signaling (LVDS) differential wire component connected to the field-programmable gate array (FPGA) decoder; and a front-end circuit board connected to the DUT circuit board and the low-voltage differential signaling (LVDS) differential wire component for capturing a signal input from the DUT circuit board and transmitting the signal input over a short-distance transmission path to minimize interferences with the signal input, before outputting a low-voltage differential signaling (LVDS) differential signal to the low-voltage differential signaling (LVDS) differential wire component, which in turn transmits the low-voltage differential signaling (LVDS) differential signal to the field-programmable gate array (FPGA) decoder; wherein the front-end circuit board is a comparator, and the comparator comprises a signal interception module for capturing the signal input from the DUT circuit board and transmitting the signal input over the short-distance transmission path to minimize the interferences with the signal input, an impedance matching module connected to the signal interception module for performing impedance matching on the signal input, a comparator module connected to the signal interception module and the low-voltage differential signaling (LVDS) differential wire component for receiving the signal input from the signal interception module and outputting the low-voltage differential signaling (LVDS) differential signal to the low-voltage differential signaling (LVDS) differential wire component, a voltage adjusting module connected to the comparator module for adjusting a reference voltage based on an input voltage of the signal input, which is compared with an input voltage, to output the low-voltage differential signaling (LVDS) differential signal to the field-programmable gate array (FPGA) decoder where corresponding decoding takes place, and an output stabilizing module connected to the comparator module for stabilizing an output voltage of the low-voltage differential signaling (LVDS) differential signal and controlling the comparator not to trigger the change to the output voltage when the input voltage of the signal input jitters around the reference voltage so as to ensure the low-voltage differential signaling (LVDS) differential signal remains unaffected.