Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels

摘要

An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.

主权项

1. A semiconductor structure with a barrier for field effect transistors with low effective mass channel materials, comprising:
a semiconductor substrate; a first source/drain layer on the semiconductor substrate; a first channel layer on the first source/drain layer; a barrier layer on the first channel layer; a second channel layer on the barrier layer, wherein the barrier layer is composed of a first semiconductor material with a lower electron affinity than a semiconductor material of the first channel layer and the second channel layer in a n-type field effect transistor; a second source/drain layer on the second channel layer; a gate electrode around a gate dielectric layer and over the gate dielectric layer on a portion of the first source/drain layer, the gate dielectric layer around at least a first dielectric spacer; a second dielectric spacer surrounding the gate electrode; a contact metal layer contacting the first source/drain layer and surrounding the second dielectric spacer; and an interlayer dielectric over the gate dielectric layer on the portion of the first source/drain layer and surrounding the contact metal layer.