Initiation of cache flushes and invalidations on graphics processors

摘要

Methods and systems may provide for receiving, at a graphics processor, a workload from a host processor and using a kernel on the graphics processor to issue a thread group for execution of the workload on the graphics processor. Additionally, one or more coherency messages may be initiated, by the graphics processor, in response to a thread-related condition of one or more caches on the graphics processor. In one example, the thread-related condition is associated with the execution of the workload on the graphics processor and indicates that the one or more caches on the graphics processor are not coherent with a system memory associated with the host processor.

主权项

1. A system comprising:
a host processor; a system memory associated with the host processor; a bus coupled to the host processor; and a graphics processor coupled to the bus, the graphics processor to receive a workload from the host processor and including,
a plurality of caches, anda kernel to issue a thread group for execution of the workload on the graphics processor in response to the graphics processor detecting a thread-related condition of one or more of the plurality of caches, wherein the graphics processor is to initiate one or more coherency messages in response to the thread-related condition of one or more of the plurality of caches, and the thread-related condition is to be associated with the execution of the workload on the graphics processor, wherein the thread group contains a plurality of threads and each of the plurality of threads includes a corresponding coherency message, and wherein the graphics processor is to enable cache coherency operations to be initiated at a kernel or sub-kernel level.