PULSE-DRIVE RESONANT CLOCK WITH ON-THE-FLY MODE CHANGE

摘要

A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.

主权项

1. A method of driving a resonant clock distribution network, the method comprising:
driving a drive point of a sector of the resonant clock distribution network with an output of at least one clock driver output stage that receives a clock input from a global clock signal; first enabling and disabling a pull-up driver of the at least one clock driver output stage in response to a first enable input; second enabling and disabling a pull-down driver of the at least one clock driver output stage in response to a second enable input; delaying the global clock signal with a delay line having a selectable delay selected in conformity with a mode select input to produce a delayed global clock signal; and controlling a clock pulse width of the clock driver output stage in conformity with the delayed global clock signal by controlling the first and second enable inputs of the at least one clock driver output by enabling the at least one clock driver output stage in response to changes in state of global clock signal and disabling the at least one clock driver output stage when the changes in state of the global clock signal have propagated through the delay line, and wherein a mode select control logic of the delay line, responsive to the mode select input, prevents the clock pulse width from enabling the at least one clock driver output stage for a duration shorter than a delay time of the delay line when the mode select input changes state.