| 摘要 |
An integrated circuit having at least one transmission port (Tx_ASIC) and at least one reception port (Rx_ASIC) and also at least one address port (ADDR; ADDR0, ADDR1), – having a memory or memory area (I, II) that has a number of memory sections (BA1, BA2) to which a piece of activation information can be written, – wherein the number of memory sections (BA1, BA2) is equal to the number, encodable by the at least one address port (ADDR; ADDR0, ADDR1), of activable integrated circuits (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') operable using a common bus, – having a control unit that is set up to compare the address encoded by the at least one address port (ADDR; ADDR0, ADDR1) with an address received at the reception port (Rx_ASIC) and, in the event of a match, to write a defined bit pattern to the memory section (BA1, BA2) associated with the address and, in the event of no match, to withhold a negative acknowledgement signal (NACK) at the transmission port (Tx_ASIC), wherein the integrated circuit (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') is set up to be activated by the defined bit pattern in the memory section (BA1, BA2) that corresponds to the address defined at the at least one address port (ADDR; ADDR0, ADDR1), in order to communicate with a microprocessor (µC) connected to the at least one transmission port (Tx_ASIC) and at least one reception port (Rx_ASIC) via the common bus. |
