发明名称 Assessment of a High Performance Computing Application in Relation to Network Latency Due to the Chosen Interconnects
摘要 A method and computer program product for testing a high performance computing application performing a computation within a clustered computer arrangement is disclosed. The high performance computing arrangement performances computations across processors in parallel wherein the processors cooperate to perform the computation. The application can be tested by adding delay and therefore latency to one or more commands inside of the precompiled application. The addition of delay can be used to simulate the performance of different interconnects that are used within the high performance computing arrangement.
申请公布号 US2017031793(A1) 申请公布日期 2017.02.02
申请号 US201615262571 申请日期 2016.09.12
申请人 Silicon Graphics International Corp. 发明人 Thomas Daniel;Baron John E.
分类号 G06F11/30;G06F11/34;G06F17/50;G06F11/36 主分类号 G06F11/30
代理机构 代理人
主权项 1. A method, in a high performance computing (HPC) arrangement comprising multiple computing nodes that cooperate to perform a computation using a switching fabric for distributing messages between the multiple computing nodes, the method comprising: measuring a first performance profile of an application pre-compiled using a first dynamically linked library for performing the computation using the multiple computing nodes on the HPC arrangement, wherein measuring the first performance profile includes recording a first time for completing an inter-node command of the pre-compiled application using a first switching fabric; simulating execution of the application on a second switching fabric by measuring a second performance profile of the pre-compiled application on the HPC arrangement, wherein measuring the second performance profile includes recording a second time for completing the inter-node command using the second switching fabric, wherein the second switching fabric is simulated by transmitting the inter-node command through the first switching fabric after introducing, by a second dynamically linked library that calls the first dynamically linked library, a delay of a predetermined time associated with the second switching fabric; and modeling an effect of the delay on performance of the pre-compiled application by comparing the first performance profile with the second performance profile.
地址 Milpitas CA US