发明名称 |
MASKING A POWER STATE OF A CORE OF A PROCESSOR |
摘要 |
In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed. |
申请公布号 |
WO2017019192(A1) |
申请公布日期 |
2017.02.02 |
申请号 |
WO2016US37347 |
申请日期 |
2016.06.14 |
申请人 |
INTEL CORPORATION |
发明人 |
GENDLER, Alexander;NOVAKOVSKY, Larisa;SISTLA, Krishnakanth V.;GARG, Vivek;MULLA, Dean;CHOUBAL, Ashish V.;HALLNOR, Erik G.;WEIER, Kimberly C. |
分类号 |
G06F1/32;G06F9/38;G06F13/14;G06F15/78 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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