METHODS OF DESIGNING A LAYOUT OF A SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR AND METHODS OF MANUFACTURING A SEMICONDUTOR DEVICE USING THE SAME

摘要

A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

主权项

1. A method of producing a layout of a semiconductor device, comprising:
providing a standard cell layout, the providing of the standard cell layout comprising creating a preliminary pin pattern of an interconnection layout of the standard cell layout; performing a routing step to produce a high-level interconnection layout in which a the preliminary pin pattern is connected to a high-level interconnection pattern; and generating a postliminary pin pattern in a region of the interconnection layout of the standard cell layout, based on hitting information obtained upon the completion of the routing step, wherein the postliminary pin pattern is smaller than the preliminary pin pattern.