| 发明名称 |
STACKED CHIP LAYOUT AND METHOD OF MAKING THE SAME |
| 摘要 |
A stacked chip layout includes a central processing chip; and a first active circuit block over the central processing chip. The stacked chip layout further includes a second active circuit block over the first active circuit. A center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block. The stacked chip layout further includes a local conductive element electrically connecting the first active circuit block to the second active circuit block. The local conductive element is within the partial overlap area. |
| 申请公布号 |
US2017032072(A1) |
申请公布日期 |
2017.02.02 |
| 申请号 |
US201615291474 |
申请日期 |
2016.10.12 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
HSU Ying-Yu |
| 分类号 |
G06F17/50;H01L23/522;H01L25/065;H01L23/528 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A stacked chip layout comprising:
a central processing chip; a first active circuit block over the central processing chip; a second active circuit block over the first active circuit, wherein a center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block; and a local conductive element electrically connecting the first active circuit block to the second active circuit block, wherein the local conductive element is within the partial overlap area. |
| 地址 |
Hsinchu TW |
